Clock driver circuit in a centrally located macro cell layout region
US5945846A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jun 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
Abstract
A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected. The sixth common line is connected to clock signal supply lines which in turn are connected to a plurality of second macro cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.