CLM/ECL clock phase shifter with CMOS digital control
US5945860A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1996 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jan 4, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CML/ECL clock phase shifter device provides a 360.degree. phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMOS current switch which generates current signals having the amplitude adjustable with the control signal, which is a digital word. Differential pairs provide amplitude modulated current signals for the input clock and the variant of the input clock. Two MOS transmission networks selectively invert each amplitude modulated signal and sum the signals from each side on a load network. The phase control resolution is optimal over four quadrants for quadrature input clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.