Analog delay circuit
US5945863A · kind A · utility
117Cited by
12References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.