Display controller with integrated half frame buffer and systems and methods using the same
US5945974A · kind A · utility
18Cited by
12References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 1996 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | May 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display controller 104 for use with a display device 107 operable to display images on a screen. Display controller 104 includes circuitry 201-210 for presenting first data to the display device 107 for generating an image in a first areas of the screen, the first data being retrieved from an external frame buffer 108. A display controller 104 further includes circuitry 205, 210 for presenting second data to the display device 107 for generating an image in the second area of the screen, the second data being retrieved from an internal frame buffer 206.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.