Nonvolatile semiconductor memory device having the reliability of gate insulating film of memory cells enhanced and method for manufacturing the same

US5946230A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Kazuhiro Shimizu · Yokohama, JP
• Seiichi Aritome · Boise, US
• Shinji Satoh · Yokohama, JP

Key dates

• Filing date: Sep 17, 1998
• Grant date: Aug 31, 1999
• Expiry date: Sep 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/49

Abstract

An EEPROM includes a memory cell array section and a peripheral driving circuit section. The memory cell array section has memory cells which are arranged in a matrix form on a silicon substrate and each of which includes a floating gate coupled to the silicon substrate via a first capacitor having a first gate insulating film as a dielectric and a control gate coupled to the floating gate via a second capacitor having a second gate insulating film as a dielectric. In the outmost portion of the memory cell array section, memory cells of a first group are arranged and memory cells of a second group are arranged in the central portion on the inner side of the memory cell array section. The first gate insulating film of the first group of memory cells is thicker than the first gate insulating film of the second group of memory cells. The peripheral driving circuit section is formed adjacent to the memory cell array section on the silicon substrate. The circuit section is to activate the storage function of the memory cell array section and includes a row decoder, sense amplifier circuit, source line potential control circuit and the like.