Dual-port memory
US5946261A · kind A · utility
7Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 1996 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | May 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-port memory includes a dummy memory cell associated with a dummy output line and with a precharge transistor, the output of the dummy cell being at "0". A dummy read transistor is turned on by the active state of the read selection signal and connects the output of the dummy cell to the dummy output line. Circuitry is provided for turning on the output transistors of the memory when the state of the dummy output line reaches a predetermined switching threshold of an inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.