RAM having multiple ports sharing common memory locations
US5946262A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having a SRAM, a DRAM and two external IO ports is provided. The SRAM has three IO ports for enabling the external IO ports and the DRAM to access each and every memory cell in the DRAM. Each SRAM cell is provided with two IO ports coupled to the external IO ports, and with an IO port for transferring data to and from the DRAM. The triple-port SRAM cell comprises three input data lines coupled to a latching circuit for writing data supplied from the external IO ports and the DRAM, and three output data lines coupled to the latching system for reading stored data to the external IO ports and the DRAM. Three write address lines and three read address lines provide addressing of the SRAM cell for data writing and reading operations performed by the external IO ports and the DRAM. Each SRAM cell may be read concurrently via all three ports to make the most current data stored in the SRAM accessible from any port at any time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.