Zero power high speed configuration memory
US5946267A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.