Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal
US5946268A · kind A · utility
37Cited by
3References
14Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 23, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jan 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.