Block-matching motion estimation apparatus under use of linear systolic array architecture
US5946405A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 6, 1996 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Dec 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/10016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block-matching motion estimation apparatus in the form of linear systolic array architecture. The apparatus includes a selecting unit for inputting data of a reference block and other data to delay the data of the reference data and selectively outputting the data; a delaying unit having P-1 delay elements where the first delay element delays and outputs an output of the selecting unit and the second to (P-1)-th delay elements delay and output outputs of just front delay element, respectively, the P-1 delay element being connected in serial; and a mean absolute difference operating unit for simultaneously inputting data of a search area to each pipe by connecting in parallel P pipes where operation elements are disposed in a linear systolic array architecture, and then calculating a value of mean absolute difference in each of the search areas by inputting outputs of the selecting unit, the first delay element, and the (P-1)-th delay element to the first pipe, the second pipe, and the (P-th) pipe, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.