Method for performing transistor-level static timing analysis of a logic circuit
US5946475A · kind A · utility
21Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jan 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for statically computing delays for transistor-level logic circuits which have input signal dependencies. This methodology may be implemented in transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.