Semiconductor wafer evaluating method and semiconductor device manufacturing method
US5946543A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 16, 1998 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jan 16, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/162
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An object is to obtain a semiconductor wafer evaluation method and a semiconductor device manufacturing method having a reduced turn-around time and requiring no process apparatus and no dielectric breakdown characteristic evaluation device in evaluation of the dielectric breakdown characteristic of the oxide film. A sample wafer (1) is etched by using an SC-1 solution bath (2) to change process defects caused in the fabrication process including mirror polishing into pits. The number of pits is detected with a dust particle inspection system, and the dielectric breakdown characteristic of the sample wafer 1 can be evaluated by using the number of detected pits and previously obtained relations between the number of pits and the dielectric breakdown characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.