Wafer level decal for minimal packaging of chips
US5946555A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1996 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Nov 4, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention includes the use of a decal to produce a packaged chip either at the chip level or wafer level. The decal includes a substrate containing circuitry that routes the chip output pads to bumps prepared for package attachment to another substrate such as a printed circuit board. The decal can be applied either to the wafer or to a single chip. The decal protects the chip and if necessary changes the interconnection density so that the chip can be interfaced with a printed circuit board or other electronic device. This configuration also may allow the packaged integrated circuit to be tested utilizing the bumps on the decal as temporary electrical contact features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.