Apparatus and method for reading data from synchronous memory
US5946712A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1997 |
| Grant date | Aug 31, 1999 |
| Priority date | — |
| Expiry date | Jun 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel apparatus and method is disclosed to assure validity of data accessed from synchronous memory during a "read" operation, wherein the synchronous memory is operating synchronously at a high frequency system clock. The invention comprises a programmable delay module which generates a skewed clock signal which is used to clock in data read from the synchronous memory. The programmable delay module generates the skewed clock signal by adding programmable time delays to the system clock signal. The inserted delay increases the data valid window time available for the "read" operation and allows sufficient setup and hold time for valid data to be read by a memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.