Device improving the processing speed of a modular arithmetic coprocessor
US5948051A · kind A · utility
6Cited by
6References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 7, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jan 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/728
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated circuit device enabling the computation of multiplication of A by B, especially a computation of the P.sub.field (A,B).sub.N type as defined in the Montgomery method, using a subdivision into words of Bt bits to carry out the different computations. This device is improved by the addition of a register of m * Bt bits containing the totality of the data element A. The invention also relates to a device for the implementation of a modular P.sub.field (A,B).sub.N operation according to the Montgomery method using the improved device presented by the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.