Multiplexing bus controller with input conditioning
US5948073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1993 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jul 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplexing bus controller with input conditioning is provided in which the need for a dedicated microprocessor for handling input filtering, input change detection and serial-to-parallel/parallel-to-serial I/O data conversion is eliminated. The controller is realized in a gate array and provides input data oversampling and output refreshing to eliminate random noise coupled to the data lines. In addition, the oversampled data is filtered to debounce the signal received from the input devices. The input data is converted from serial-to-parallel and checked to detect any change from the previous input data stream. Upon detection of an input change, the host microprocessor is interrupted. When the host microprocessor sends data to the bus controller, the bus controller then converts the data to a serial stream for communication to the appropriate output device. Additionally, the bus controller is provided with an internal turnaround circuit to loop back outputs to the inputs for diagnostic purposes. Very low gate counts realized in the design of the multiplexing bus controller allow it to be realized on a single chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.