Method and circuit for reducing power and/or current consumption
US5949261A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (e.g., a zero-delay buffer) is provided which is capable of reducing current or power consumption without the use of a dedicated pin. The device may include a frequency detector that receives a detector input signal corresponding to or derived from a device input signal. The device input signal performs a first function during normal operation of the device. The detector determines whether the frequency of the detector input signal is less than a predetermined minimum, and if so, generates a power down signal configured to direct the device to reduce current or power consumption in at least one of its component circuits. The frequency detector may include a "one-shot" circuit responsive to the detector input signal for generating a frequency indicator signal, and a "power down" signal output circuit responsive to the frequency indicator signal for generating the power down signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.