Variable delay circuit for varying delay time and pulse width
US5949268A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.