Self aligning PLL demodulator
US5949281A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A demodulator (200) including a phase detector (201) receiving a modulated signal and outputting a demodulated signal. The phase detector (201) also receives a reference signal. A programmable voltage circuit (203, 204) outputs an analog voltage. A reference signal generator (208) that is responsive to the programmable voltage circuit (204) and the demodulated signal has an output coupled to provide the reference signal to the phase detector (201). A window detect circuit (206) with an input coupled to the demodulated signal generates an inhibit signal when the demodulated signal is within preselected limits. The inhibit signal is coupled to latch the programmable voltage circuit (203, 204). Preferably, the programmable voltage circuit is implemented as a digital-to-analog converter (204) driven by a counter (203) or by a processor circuit (302).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.