Memory device with current limiting feature
US5949729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jul 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to "L" level. An inverter provides a sense activating signal of "H" level to an NMOS device, while another inverter provides a sense activating signal of "L" level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the "L" level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.