Processing asynchronous data within a set-top decoder
US5949795A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Feb 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/23406
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Data overflow in a buffer of a set-top decoder for receiving asynchronous data, such as digital television signals, is prevented while also maintaining compliance with an interface timing standard such as the RS404-A standard. A fullness level of the buffer is monitored to determine whether the fullness falls within a first, nominal range, or into second or third higher ranges. A clocking signal is derived from a ratio of a fixed reference clock signal and a divisor for outputting asynchronous data from the buffer at a desired rate. A direct digital synthesis (DDS) circuit may be used to provide a fractional divisor. The divisor is selected to provide the clocking signal at a rate so that a difference between a target output rate and the actual output rate falls within a data performance standard such as the RS404-A standard.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.