Deadlock avoidance in a bridge between a split transaction bus and a single envelope bus
US5949981A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jul 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for avoiding deadlock, in particular, a Read/Read deadlock, in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, deadlock is avoided using a closely-coupled master and slave circuit on the split-response bus. The closely-coupled master and slave circuit operates to disallow a second deadlocking read transaction. While there is an outstanding read transaction in either the master or slave portions of the split-response bus interface, the other portion will refuse to accept, or retry, another potentially deadlocking read transaction. The invention has the advantage of being absolutely certain of avoiding the Read/Read deadlock condition with a minimum amount of circuit complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.