Method for compiling loops containing prefetch instructions that replaces one or more actual prefetches with one virtual prefetch prior to loop scheduling and unrolling
US5950007A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1996 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jul 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Prefetch instructions having a function to move data to a cache memory from main memory are scheduled simultaneously with execution of other instructions. The prefetch instructions are scheduled by replacing, with the original prefetch instructions, the virtual prefetch instructions obtained by unrolling a kernel section of the schedule constituted by generating a dependency graph having dependent relationships between the prefetch instruction and the memory reference instruction, and then applying the software pipelining thereto, or by further unrolling the kernel section of the constituted schedule to delete the redundant prefetch instructions, or further by applying the software pipelining to the dependency graph which is formed by combining a plurality of prefetch instructions and replacing the prefetch instructions with virtual prefetch instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.