Self-adjusting semiconductor package stand-offs
US5950073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Sep 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/341
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure that includes placing self-adjusting stand-offs between the substrate and sealband of the cap, such that the gap between the cap and the chip can be controlled, thereby improving the thermal and fatigue performance of the overall package. The height of the stand-off is varied by controlling the application (i.e., the temperature and the timing) of the heat that is used by the soldering process normally used in the generation of solder joints. The control of the soldering procedure is calibrated to optimize the amount of the stand-off which is dissolved, melted and spalled until the optimum height of the stand-off is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.