Method for fabricating air-insulated multilevel metal interconnections for integrated circuits
US5950102A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Feb 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making air-insulated planar metal interconnections having low interlevel capacitance with improved RC time delays for integrated circuits is achieved. The method involves using a multilayer of negative and positive photoresists in which open regions are developed in the negative photoresist for the metal interconnections, and open regions are developed in the positive photoresist for via holes. The open regions are then filled with a Ti/TiN diffusion barrier deposited at room temperature and an electroless plated copper, and polished back using a Dual Damazene to form the interconnecting metal level and the via hole stud. The method is repeated several times to form multilevel metal interconnections. The remaining photoresist is then totally removed by oxygen ashing to leave a free-standing multilevel metal interconnection structure that is conformally coated with a thin Al.sub.2 O.sub.3 passivation layer and having air insulation. This results in a much lower inter- and intralevel capacitance and improved circuit performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.