Cacheable interface control registers for high speed data transfer
US5951657A · kind A · utility
9Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Jun 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.