Bus protocol violation monitor systems and methods
US5951661A · kind A · utility
10Cited by
11References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system employing a bus protocol violation monitor system and method. The monitor system includes a bus wait timer logic circuit which comprises a state machine that receives a portion of the bus interface control signals, a programmable timer module and a plurality of data selectors that are actuatable responsive to a control input. In addition to storing the violation information in a register, the system provides for interrupts with graded levels of priorities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.