Multiprocessor system and its control method
US5951683A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One of processors connected effectively to a system is allocated to a master processor and the other remaining processors are allocated to slave processors. Each processor compares the self processor number of a processor number register and the processor number of the other processor of a processor effective register. For example, when the self processor number is smallest as compared with the other processor numbers, it is recognized that the self processor is a master processor. A master initialization diagnosing process after completion of the allocation is monitored by the slave processor. When an abnormality of the master processor is recognized, a degeneration to disconnect the master processor from the system is executed and is again reconstructed by the allocating process of master/slaves. Even when an abnormality occurs in the master processor, the operation in which the system was degenerated can be executed until the minimum construction in which two or more processors normally operate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.