Monolithically integrated planar semi-conductor arrangement with temperature compensation

US5952705A · kind A · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Hartmut Michel
• Christian Pluntke · Hechingen, DE
• Alfred Goerlach · Tübingen, DE

Key dates

• Filing date: Jan 9, 1998
• Grant date: Sep 14, 1999
• Expiry date: Jan 9, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/105

Abstract

A semiconductor, where a region is introduced into a semiconductor substrate and, together with this substrate, forms a p-n junction. Provision is made in the vicinity of the space charge region being formed for a covering electrode and a heavily doped region. The covering electrode is coupled to a voltage divider, through which the potential of the covering electrode is adjusted with temperature compensation.