Multiple logic family compatible output driver
US5952847A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1996 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter. In the second embodiment of the present invention, the P-Channel MOS pullup transistor is turned on by a ground level signal from the level shifter. The enable logic drives the output of the totem pole in response to input signals to the enable logic. The inputs to the enable logic are…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.