Fast wide decode in an FPGA using probe circuit
US5952852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Jul 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318519
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a first aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a test probe circuit associated with a column in the array, selecting at least one logic module associated with the test probe circuit, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred. In a second aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a plurality of test probe circuits, each associated with a column in the array, selecting at least one logic module associated with each of the test probe circuits, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.