Exponentiator circuit and method for generating decibel steps of programmable current gain
US5952867A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Nov 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An exponentiator circuit (24) is provided that includes a first transistor device, that includes a BJT (80) and a BJT (84) configured in a Darlington configuration, and a second transistor device that includes a BJT (88) and a BJT (92) also configured in a Darlington configuration. The first transistor device is coupled between a reference voltage and a summing node, while the second transistor device is coupled between an output node and a summing node. A programmable current iI is provided to the first transistor device and the second transistor device such that the base-to-emitter voltages of the two devices are provided at a different level. This results in the generation of a first current through the first transistor device and an output current through the second transistor device. An input current is provided at the summing node which is equivalent to the sum of the first current and the output current. The overall gain of the exponentiator circuit (24) is approximately exponential. The exponentiator circuit (24) may have its overall gain varied based on the value of the programmable current iI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.