ESD protection circuit for I/O buffers

US5953190A · kind A · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• David B. Rees · Dudley, GB
• James Lutley · Southampton, GB
• Sandeep Pant · Basingstoke, GB

Key dates

• Filing date: May 2, 1997
• Grant date: Sep 14, 1999
• Expiry date: May 2, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/60

Abstract

An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.