Multi-port SRAM with reduced access requirements
US5953283A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Jul 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved multi-port SRAM that requires fewer access means, bit lines and sense amplifiers for multiport access. The number of access means can be reduced to ceiling (log.sub.2 B), where B is the number of access ports. The number of bit line sense amplifiers needed to achieve multiport access can also be reduced by the same factor as the number of access devices per cell. An efficient means is provided to select a correct access device among the plurality of access devices within the array and to condition a correct multiplexer select signal to couple a correct bit as specified by the port read address to the port read output. The access device selection can be implemented by a tree representation of all possible bit line and multiplexer select combinations. The tree representation can be implemented in hardware or software. Examples are provided of both a circuit and a tree walking algorithm that gives priority by port order. Alternatively, logic to select the bit lines and controls could give priority in bit order. In either case, examples are provided for modifying the strict priority order to avoid conflicts and obtain a correct solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.