High speed clock recovery circuit using complimentary dividers
US5953386A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 1996 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Jun 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.