Multiprocessor interface adaptor with broadcast function
US5953509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | May 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/493
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An telephone media processing server is described having clock pulse steering circuit for steering clock pulses to a plurality of digital processors under control of a main processor. Other signals, such as a frame clock, for generating frame pulses, address and data lines are distributed using single conductors connected to output pins of a control processor. Typically, more than eight signal processors partitioned in a plurality of groups are interfaced to a single main processor. Each group of signal processors has a clock input controlled by the clock steering circuit. A main processor has a data port pin, an address port pin, and a switching command output connected to the clock pulse steering means for steering clock pulses to each group of processors. The signal processors set the data pin and address pin to a high impedance when the clock input is inactive. An example using the TMS320C5x processor is detailed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.