Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step
US5953614A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1997 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Oct 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.