Single-chip DBS receiver
US5953636A · kind A · utility
31Cited by
23References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1996 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Oct 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.