Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address
US5954815A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Jan 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predict…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.