Method for isolating faults on a clocked synchronous bus
US5954825A · kind A · utility
15Cited by
17References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Apr 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2268
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a "check stop" signal. Once frozen, the shift register can be scanned for fault isolation analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.