Data storage system having row/column address parity checking
US5954838A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit. Each one of the memory units includes: a buffer memory coupled to the bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the interna…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.