Signal generator with synchronous mirror delay circuit
US5955905A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Nov 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock signal received from an external terminal through an input buffer is delayed by delay circuits. A counter circuit is started up in accordance with the clock signal transmitted through the delay circuits to count an oscillation pulse having a frequency which is sufficiently high with respect to that of the clock signal. Further, the counter circuit reversely counts the count in response to a clock signal delayed by one cycle, which has passed through the input buffer. When its count once again reaches the counter value at the start of counting, the counter circuit generates an output timing signal and transmits it to an internal circuit through a clock driver. A delay time outputted from the delay circuits is set to a delay time corresponding to the sum of a delay time of the input buffer and a delay time of the clock driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.