On-chip differential resistance technique with noise immunity and symmetric resistance
US5955911A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Oct 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.