Multiplexer circuits
US5955912A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Oct 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer has first, second, third and fourth inputs receiving respective first, second, third and fourth input signals, having first and second control inputs receiving respective first and second select input signals and an output. Each of the four input signals is supplied to the input of a CMOS transmission gate. The first and second transmission gates are clocked via the first select signal and its inverse in a first phase. The third and fourth transmission gates are clocked via the first select signal and its inverse in a second phase, opposite to the first phase. A first embodiment includes a first intermediate inverter having an input connected jointly to the outputs of the first and second transmission gates and a second intermediate inverter having an input connected jointly to the outputs of the third and fourth transmission gates. The multiplexer output is provides by a fifth and a sixth transmission gate oppositely clocked via the second control signal input and coupled to the first and second intermediate inverters, respectively. A second embodiment employs double pass logic in place of the fifth and sixth transmission gates and an output inverter. A third embodim…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.