ROM-based control units in a geometry accelerator for a computer graphics system
US5956047A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Apr 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.