Method and apparatus for optimizing a circuit design having multi-paths therein
US5956256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.