Circuit arrangement for digital multiplication of integers
US5956264A · kind A · utility
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6References
5Claims
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Key dates
| Filing date | Jan 18, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Jan 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2101/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for digital multiplication of integers, having an encoding unit, an adding unit, which adds the output values of the encoding unit, and a decoding unit, which decodes the output value of the adding unit. The encoding unit encodes the numbers according to the following formula: EQU X=2.sup.k * (1+X.sub.B)=2.sup.k +X.sub.B EQU Y=2.sup.l * (1+Y.sub.B)=2.sup.l +Y.sub.B The adding unit adds the values k, 1 and x and y, and the mixed terms X.sub.B * Y.sub.B depending on the desired accuracy being either not formed or recursively calculated according to the preceding manner of procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.