Semiconductor memory device capable of setting substrate voltage shallow in disturb test mode and self refresh mode
US5956281A · kind A · utility
14Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1998 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Mar 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A switching circuit is provided which activates a shallow level detector and inactivates a deep level detector when a disturb test signal or a self refresh signal is activated. Accordingly, a shallow substrate voltage at the same level as a detection level of the shallow level detector can be generated by a substrate voltage generating circuit not only in a disturb test mode but also in a self refresh mode. As a result, the area penalty due to the shallow level detector is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.