Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns
US5956476A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus. First storage circuitry stores a record of the first detection signal having been asserted. Second storage circuitry stores the transaction identifying indicia present on the bus when the first signal pattern is detected. Secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.