Intermediate-grain reconfigurable processing device
US5956518A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Apr 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.